The operation of an integrated circuit memory device may be controlled by various control signals. For example, in a data read operation of an integrated circuit memory device, memory cells belonging to a specific row may be selected according to a word line enable signal from a plurality of memory cells arranged in a matrix form, data transmitted from a memory cell belonging to a specific column among the memory cells of the specific row may be selected according to a column select line enable signal, and data read from the memory cells may be output in synchronization with a first read pulse signal output from an input/output sense amplifier after a predetermined time has elapsed from when the column select line enable signal is enabled.
In order to stabilize the operation of an integrated circuit memory device, it may be advantageous to maintain predetermined timing gaps between control signals. That is, control signals involved in a specific operation of the integrated circuit memory device may be enabled to provide a time lag between signals corresponding to one or more predetermined timing gaps. When a predetermined timing gap is not maintained between the control signals, that is, when timing characteristics are poor, stable operation of the integrated circuit memory device may not be guaranteed. The timing characteristics may be sensitive to the operating environment of the integrated circuit memory device, and thus variations in the operating environment of the integrated circuit memory device may contribute to errors in data read operations and/or data write operations.
As the operating speed of the integrated circuit memory device is increased, the timing characteristics may increasingly affect the performance of the integrated circuit memory device. Thus, the timing characteristics may significantly influence the performance of the integrated circuit memory device when the operating speed of the integrated circuit memory device is increased.
Accordingly, it may be desirable to reduce and/or prevent performance degradation of the integrated circuit memory device that may be caused by instability of the timing characteristics. In order to achieve this, the current timing gap between control signals may be correctly measured, and the timing gap between the control signals may be controlled based on the measurement result. As such, various methods for controlling timing gaps between control signals have been proposed. One such method is described in U.S. Pat. No. 6,252,820, entitled “Semiconductor memory device capable of monitoring and adjusting the timing and pulse width of internal control signals”.